Semiconductor device containing HEMT and MISFET and method of forming the same

ABSTRACT

A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

PRIORITY CLAIM AND CROSS-REFERENCE

The present application is a continuation of U.S. application Ser. No. 15/224,263, entitled “Semiconductor Device Containing HEMT and MISFET and Method of Forming the Same,” filed on Jul. 29, 2016, which application is a divisional of U.S. application Ser. No. 14/515,392, entitled “Semiconductor Device Containing HEMT and MISFET and Method of Forming the Same,” filed on Oct. 15, 2014, now U.S. Pat. No. 9,418,901, issued Aug. 16, 2016, which application is a continuation of U.S. application Ser. No. 13/777,701, entitled “Semiconductor Device Containing HEMT and MISFET and Method of Forming the Same,” filed on Feb. 26, 2013, now U.S. Pat. No. 8,912,573, issued Dec. 16, 2014, all of which are incorporated herein by reference.

TECHNICAL FIELD

This disclosure relates generally to a semiconductor structure and, more particularly, to a joint high electron mobility transistor (HEMT) and metal-insulator-semiconductor field-effect transistor (MISFET) semiconductor structure, and method for forming this semiconductor structure.

BACKGROUND

In semiconductor technology, due to their characteristics, Group III-Group V (or III-V) semiconductor compounds are used to form various integrated circuit devices, such as high power field-effect transistors, high frequency transistors, or high electron mobility transistors (HEMTs). A HEMT is a field effect transistor incorporating a junction between two materials with different band gaps (i.e., a heterojunction) as the channel instead of a doped region, as is generally the case for metal oxide semiconductor field effect transistors (MOSFETs). In contrast with MOSFETs, HEMTs have a number of attractive properties including high electron mobility, the ability to transmit signals at high frequencies, etc.

From an application point of view, enhancement-mode (E-mode) HEMTs have many advantages. E-mode HEMTs allow elimination of a negative-polarity voltage supply, and, therefore, reduction of the circuit complexity and cost. Despite the attractive properties noted above, a number of challenges exist in connection with developing III-V semiconductor compound-based devices. Various techniques directed at configurations and materials of these III-V semiconductor compounds have been implemented to try and further improve transistor device performance.

Frequently, layers of a semiconductor are doped in the manufacturing process. Magnesium (Mg) is a common dopant for a P-type gallium nitride (p-GaN). Mg diffuses into active layers and impacts performance, specifically in the 2-dimensional electron gas (2DEG) and current density of HEMT devices.

Therefore, the process for making semiconductor structures containing HEMT and MISFET devices need to be improved continuous to ensure high level performance and production yield.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure may be understood from the following detailed description and the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a cross-sectional view of a semiconductor structure having both a high electron mobility transistor (HEMT) and metal-insulator-semiconductor field-effect transistor (MISFET) regions, according to one or more embodiments of this disclosure.

FIG. 2 is a flowchart of a method of forming a semiconductor structure having both a HEMT and a MISFET according to one or more embodiments of this disclosure.

FIGS. 3 to 11 are cross-sectional views of a semiconductor structure having a HEMT at various stages of manufacture according to one embodiment of the method of FIG. 2.

DETAILED DESCRIPTION

The making and using of illustrative embodiments are discussed in detail below. It should be appreciated, however, that the disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

A plurality of semiconductor chip regions is marked on the substrate by scribe lines between the chip regions. The substrate will go through a variety of cleaning, layering, patterning, etching and doping steps to form integrated circuits. The term “substrate” herein generally refers to the bulk substrate on which various layers and device structures are formed. In some embodiments, the bulk substrate includes silicon or a compound semiconductor, such as GaAs, InP, SiGe, or SiC. Examples of such layers include dielectric layers, doped layers, polysilicon layers, diffusion barrier layers, or conductive layers. Examples of device structures include transistors, resistors, and/or capacitors, which may be interconnected through an interconnect layer to additional integrated circuits.

FIG. 1 is a cross-sectional view of a semiconductor structure 100 having both a high electron mobility transistor (HEMT) and metal-insulator-semiconductor field-effect transistor (MISFET) according to one or more embodiments of this disclosure.

Referring to FIG. 1, the semiconductor structure 100 having both a HEMT and a MISFET is illustrated. The semiconductor structure 100 includes a substrate 102. In some embodiments, the substrate 102 includes a silicon carbide (SiC) substrate, sapphire substrate or a silicon substrate.

The semiconductor structure 100 also includes a heterojunction formed between two different semiconductor material layers, such as material layers with different band gaps. For example, the semiconductor structure 100 includes a non-doped narrow-band gap channel layer and a wide-band gap n-type donor-supply layer. In at least one embodiment, the semiconductor structure 100 includes a first III-V compound layer (or referred to as a buffer layer) 104 formed on the substrate 102 and a second III-V compound layer (or referred to as a donor-supply layer) 106 formed on the channel layer 104. The channel layer 104 and the donor-supply layer 106 are compounds made from the III-V groups in the periodic table of elements. However, the channel layer 104 and the donor-supply layer 106 are different from each other in composition. The channel layer 104 is undoped or unintentionally doped (UID). In the present example of the semiconductor structure 100, the channel layer 104 includes a gallium nitride (GaN) layer (also referred to as the GaN layer 104). The donor-supply layer 106 includes an aluminum gallium nitride (AlGaN) layer (also referred to as AlGaN layer 106). The GaN layer 104 and AlGaN layer 106 directly contact each other. In another example, the channel layer 104 includes a GaAs layer or InP layer. The donor-supply layer 106 includes an AlGaAs layer or an AlInP layer.

The GaN layer 104 is undoped. Alternatively, the GaN layer 104 is unintentionally doped, such as lightly doped with n-type dopants due to a precursor used to form the GaN layer 104. In one example, the GaN layer 104 has a thickness in a range from about 0.5 microns to about 10 microns.

The AlGaN layer 106 is intentionally doped. In one example, the AlGaN layer 106 has a thickness in a range from about 5 nanometers (nm) to about 50 nm.

The semiconductor structure 100 also includes at least two sets of source features and drain features (132/134 and 136/138, respectively disposed on the AlGaN layer 110. Each of the source feature and the drain feature comprises a metal feature. In one example, the metal feature is free of Au and comprises Al, Ti, or Cu. Each set of these source features is placed in a respective MISFET or HEMT region of the semiconductor structure 100.

The semiconductor structure 100 further includes a dielectric cap layer 112 disposed on a top surface of the AlGaN layer 110 not occupied by the metal features. In the MISFET region of the semiconductor structure 110, the dielectric cap layer 112 fills an opening that exposes a portion of the AlGaN layer 110 for a gate electrode formation. The dielectric cap layer 112 protects the underlying AlGaN layer 110 from damage in the following process having plasma.

In some embodiments, the semiconductor structure 100 further includes a protection layer 118. The protection layer is disposed on top surfaces of the metal features (132/134 and 136/138) and under the gate dielectric layer 122. The protection layer further includes an opening that aligns with the opening in the dielectric cap layer 112. The combined opening of the opening in the protection layer and the opening in the dielectric cap layer 112 exposes the portion of the AlGaN layer 110 for the gate electrode formation. The protection layer also covers the source feature and the drain feature, and prevents the source feature and the drain feature from exposure during an annealing process in the formation of the isolation regions 116.

On the MISFET side of the semiconductor structure 100, it also includes a gate electrode 130 disposed on the opening over AlGaN layer no between the source and drain features. The gate electrode 130 includes a conductive material layer configured for voltage bias and electrical coupling with the carrier channel. In this embodiment, the conductive material is disposed on top of a gate dielectric layer 122. In various examples, the conductive material layer includes a refractory metal or its compounds, e.g., titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW) and tungsten (W). In another example, the conductive material layer includes nickel (Ni), gold (Au) or copper (Cu).

On the HEMT side of the semiconductor structure 100, it includes a gate electrode 128 disposed on the opening over AlGaN layer 110 between the source and drain features. Here, since there is no gate dielectric layer 122 disposed in the opening above AlGaN layer 110, the gate electrode 128 is in direct contact with the AlGaN layer no. The gate electrode 128 also includes a conductive material layer configured for voltage bias and electrical coupling with the carrier channel. In various examples, the conductive material layer includes a refractory metal or its compounds, e.g., titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW) and tungsten (W). In another example, the conductive material layer includes nickel (Ni), gold (Au) or copper (Cu).

In the above described embodiments, the gate electrode 128 and 130, the source/drain features, and the carrier channel in the GaN layer 106 are configured as a transistor. When a voltage is applied to the gate stack, a device current of the transistor could be modulated.

FIG. 2 is a flowchart of a method 200 of forming a semiconductor structure having a HEMT and a MISFET according to one or more embodiments of this disclosure. Referring now to FIG. 2, the flowchart of the method 200, at operation 201, a first III-V compound layer is provided. The first III-V compound layer is formed on a substrate. Next, the method 200 continues with operation 202 in which a second III-V compound layer is epitaxially grown on the first III-V compound layer. The method 200 continues with operation 203 in which a third III-V compound layer is epitaxially grown on the second III-V compound layer. The method 200 continues with operation 204 in which a source feature and a drain feature are formed on the third III-V compound layer. The method 200 continues with operation 205 in which a gate dielectric layer is deposited on a portion of the third III-V compound layer. The method 200 continues with operation 206 in which a gate electrode is formed on the gate dielectric layer between the source feature and the drain feature in the MISFET region of the semiconductor structure. It should be noted that additional processes may be provided before, during, or after the method 200 of FIG. 2.

FIGS. 3 to 10 are cross-sectional views of the semiconductor structure 100 having both HEMT and MISFET structures at various stages of manufacture according to various embodiments of the method 200 of FIG. 2. Various figures have been simplified for a better understanding of the inventive concepts of the present disclosure.

Referring to FIG. 3, which is an enlarged cross-sectional view of a portion of a substrate 102 of a semiconductor structure 100 after performing operations 201, 202 and 203. In some embodiments, the substrate 102 includes a silicon carbide (SiC) substrate, sapphire substrate or a silicon substrate. A first III-V compound layer 104, also referred to as a buffer layer, is grown on the substrate 102. In the embodiment of FIGS. 3-10, the first III-V compound layer 104 refers to a gallium nitride (GaN) layer (also referred to as the GaN layer 104). The GaN layer 104 can be epitaxially grown by metal organic vapor phase epitaxy (MOVPE) using gallium-containing precursor and nitrogen-containing precursor. The gallium-containing precursor includes trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemical. The nitrogen-containing precursor includes ammonia (NH₃), tertiarybutylamine (TBAm), phenyl hydrazine, or other suitable chemical. In the embodiment of FIGS. 3-10, the GaN layer 104 has a thickness in a range from about 0.5 micron to about 10 microns. In other embodiments, the first III-V compound layer 104 may include a GaAs layer or AlN layer.

A second III-V compound layer 106, also referred to as donor-supply layer, is grown on first III-V compound layer (i.e., the buffer layer) 104. In at least one embodiment, the second III-V compound layer 106 refers to an aluminum gallium nitride (AlGaN) layer (also referred to as the AlGaN layer 106). In the embodiment of FIGS. 3-10, the AlGaN layer 106 is epitaxially grown on the AlN buffer layer 104 by MOVPE using aluminum-containing precursor, gallium-containing precursor, and nitrogen-containing precursor. The aluminum-containing precursor includes trimethylaluminum (TMA), trimethylaluminum (TEA), or other suitable chemical. The gallium-containing precursor includes TMG, TEG, or other suitable chemical. The nitrogen-containing precursor includes ammonia, TBAm, phenyl hydrazine, or other suitable chemical. In the embodiment of FIGS. 3-10, the AlGaN layer 106 has a thickness in a range from about 5 nanometers to about 50 nanometers. In other embodiments, the second III-V compound layer 106 may include an AlGaAs layer, or AlInP layer.

Further, the second III-V compound layer 106 may include an InGaN diffusion barrier layer. The InGaN diffusion barrier layer may be grown at a range of about 300 mbar to about 500 mbar and in a range of about 700° C. to about 900° C. The Indium composition of the InGaN diffusion barrier layer 130 may be in a range from about 5% to about 10%.

Thereafter, a P-type GaN layer 108 is disposed onto the second III-V compound layer 106. Then, a second AlGaN layer 110 is disposed onto the P-type GaN layer 108.

Next, a dielectric cap layer 112 is deposited on a top surface of the second AlGaN layer 110, and over the top surface of the P-type GaN 108 (as shown in FIG. 4). In the embodiment of FIGS. 3-10, the dielectric cap layer 112 has a thickness in a range from about 100 Å to about 5000 Å. In some embodiments, the dielectric cap layer 112 includes SiO₂ or Si₃N₄. In one example, the dielectric cap layer 112 is Si₃N₄ and is formed by performing a low pressure chemical vapor deposition (LPCVD) method without plasma using SiH₄ and NH₃ gases. An operation temperature is in a range of from about 650° C. to about 800° C. An operation pressure is in a range of about 0.1 Torr and about 1 Torr. The dielectric cap layer 112 protects the underlying second AlGaN layer 110 from damage in the following processes having plasma. Next, as FIG. 4 shows, two openings in the dielectric cap layer 112 are defined by lithography and etching processes to expose two openings in the second AlGaN, III-V compound, layer 110.

Next, as shown in FIG. 5, a metal layer is deposited over the dielectric cap layer 112, which overfills the two openings and contacts the second AlGaN III-V compound layer 110. A photoresist layer (not shown) is formed over the metal layer and developed to form a feature over each of the two openings. The metal layer not covered by the feature of the photoresist layer is removed by a reactive ion etch (RIE) process that etches the exposed portions of the metal layer down to the underlying the dielectric cap layer 112. Two metal features 114 and 116 are generated after the etching process. The metal features 114 and 116 are configured as the source feature or the drain feature for the MISFET and the HEMT, respectively. The photoresist layer is removed after the formation of the metal features 114 and 116. The dielectric cap layer 112 protects the underlying second AlGaN III-V compound layer 110 from damage during the etching process to form metal features 114 and 116.

In some embodiments, the metal layer of the metal features 114 and 116 includes one or more conductive materials. In at least one example, the metal layer is free of gold (Au) and comprises titanium (Ti), titanium nitride (TiN), or aluminum copper (AlCu) alloy. In another example, the metal layer includes a bottom Ti/TiN layer, an AlCu layer overlying the bottom Ti/TiN layer, and a top Ti layer overlying the AlCu layer. The formation methods of the metal layer include atomic layer deposition (ALD) or physical vapor deposition (PVD) processes. Without using Au in the metal features 114 and 116, the method 200 could also be implemented in the production line of integrated circuits on silicon substrate. The contamination concern from Au on the silicon fabrication process could be eliminated.

Next, as FIG. 6 shows a protection layer 118 is optionally deposited on top surfaces of the metal features 114 and 116 and the dielectric cap layer 112. In some embodiments, the protection layer includes dielectric materials such as SiO₂ or Si₃N₄. In one example, the protection layer is Si₃N₄ and is formed by performing a plasma enhanced chemical vapor deposition (PECVD) method.

FIG. 7 illustrates the structure 100 after forming an opening 120 in the dielectric cap layer 112 (also in the protection layer 118). Specifically, a patterned mask layer (not shown) is formed on a top surface of the dielectric cap layer 112 and an etching process is performed to remove a portion of the dielectric cap layer 112 (also remove a portion of the protection layer if the protection layer exists). The opening 120 exposes a portion of the top surface of the second AlGaN III-V compound layer no. The opening 116 is configured as a location for the later gate electrode formation. It is important to note that, in this embodiment, the opening 120 is formed in the MISFET region of the semiconductor structure, while the HEMT region of the semiconductor structure is covered by a patterned mask.

FIG. 8 illustrates the structure 100 after depositing a gate dielectric layer 122 in operation 204. The gate dielectric layer 122 is deposited on the dielectric cap layer 112, along an interior surface of the opening 120 and on the exposed portion of the second AlGaN III-V compound layer 110 in the MISFET region. The gate dielectric layer 122 is also deposited over the source feature and the drain feature. In some embodiments, the gate dielectric layer 122 is in a thickness range from about 3 nm to about 20 nm. In some examples, the gate dielectric layer 122 comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide. In one embodiment, the gate dielectric layer 122 is formed by an atomic layer deposition (ALD) method. The ALD method is based on the sequential use of a gas phase chemical process. The majority of ALD reactions use two chemicals, typically called precursors. These precursors react with a surface one-at-a-time in a sequential manner. By exposing the precursors to the growth surface repeatedly, the gate dielectric layer 122 is deposited. The ALD method provides a uniform thickness of the gate dielectric layer 122 with high quality. In one example, the gate dielectric layer 118 is zirconium oxide. In some embodiments, a first precursor includes tetrakis[ethylmethylamino]zirconium (TEMAZr) or zirconium chloride (ZrCl₄). In some embodiments, a second precursor includes oxygen in order to oxidize the first precursor material to form a monolayer. In some examples, the second precursor includes ozone (O₃), oxygen, water (H₂O), N₂O or H₂O—H₂P₂. In other embodiments, the gate dielectric layer 122 is formed by a plasma enhanced chemical vapor deposition (PECVD) or a low pressure chemical vapor deposition (LPCVD).

Next, as FIG. 9 illustrates, an opening 124 is formed in the HEMT region of the dielectric cap layer 112 (also in the protection layer 118). Note that opening 124 in the HEMT region of the semiconductor structure is formed while the HEMT region is covered by a mask. A patterned mask layer (not shown) is formed on a top surface of the dielectric cap layer 112 in the HEMT region, and an etching process is performed to remove a portion of the dielectric cap layer 112 (also remove a portion of the protection layer 118). The opening 124, therefore, exposes a portion of the top surface of the second AlGaN III-V compound layer 110 in the HEMT region. The opening 122 is configured as a location for the later gate electrode formation in the HEMT region. In essence, the embodiment requires forming HEMT and MISFET gates separately.

FIG. 10 illustrates the structure 100 after performing operation 206, which forms a conductive material layer 126 over the entire MISFET and HEMT regions. In various examples, the conductive material layer 126 includes a refractory metal or its compounds, e.g., titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW) and tungsten (W). In another example, the conductive material layer 126 includes nickel (Ni), gold (Au) or copper (Cu). The conductive material layer 126 overfills the opening 124 in the HEMT region. The conductive material lies on top of the portion of the dielectric cap layer 112, which had filled the opening 120 in the MISFET region.

Next, as FIG. 11 shows, gate electrodes 128 and 130 are formed above portions of the second AlGaN III-V compound layer 110. Lithography and etching processes are performed on the gate electrode layer to define the gate electrodes 128 and 130 in the HEMT and MISFET regions, respectively. Specifically, in this step of the process, the conductive material layer and the underlying dielectric layer 122 are removed across both the MISFET and HEMT regions in the semiconductor structure. Thereafter, each of the gate electrodes 128 and 130 is formed between the source and drain features of the respective HEMT and MISFET regions. In some embodiments, the gate electrode 128 includes a conductive material layer that includes a refractory metal or its compounds, e.g., titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW) and tungsten (W). In another example, the gate electrodes 128 and 130 includes nickel (Ni), gold (Au) or copper (Cu).

Various embodiments of the present disclosure may be used to improve the performance of a semiconductor structure having a HEMT and MISFET. For example, in conventional process methods for making semiconductor structures containing HEMT and MISFET, after dielectric layer is deposited onto the structure, it is removed alternately in the MISFET and HEMT regions. In contrast, in the embodiments of this invention, the dielectric layer is removed simultaneously across both the HEMT and MISFET regions.

According to an embodiment, a method comprises forming a stack of semiconductor layers over a substrate, each semiconductor layer in the stack of semiconductor layers having a different band gap than an adjacent semiconductor layer in the stack of semiconductor layers, and forming a capping layer over the stack of semiconductor layers, the capping layer comprising a first source opening, a first drain opening, a second source opening, and a second drain opening. The method further comprises simultaneously forming first and second source and drain features in the respective first and second source and drain openings, forming a first gate opening between the first source feature and the first drain feature, and forming a gate dielectric layer in the first gate opening. The method further comprises forming a second gate opening between the second source feature and the second drain feature, and simultaneously forming a gate electrode layer in the first gate opening and the second gate opening.

According to another embodiment, a method comprises forming a stack of semiconductor layers over a substrate, each semiconductor layer in the stack of semiconductor layers having a different band gap than an adjacent semiconductor layer in the stack of semiconductor layers, and forming a capping layer over the stack of semiconductor layers, the capping layer including a first source opening, a first drain opening, a second source opening, and a second drain opening. The method further comprises simultaneously forming first and second source and drain features in the respective first and second source and drain openings, and forming a protection layer over the capping layer, the protection layer including a first gate opening and a second gate opening, wherein the first gate opening and the second gate opening extend through the capping layer. The method further comprises forming a gate dielectric material in the first gate opening, and forming a gate electrode layer in the first gate opening and the second gate opening.

According to yet another embodiment, a method comprises epitaxially growing a second III-V compound layer over a first III-V compound layer, the second III-V compound layer having a different band gap than the first III-V compound layer, epitaxially growing a third III-V compound layer over the second III-V compound layer, and forming a dielectric layer over the third III-V compound layer, the dielectric layer including a first source opening, a first drain opening, a second source opening, and a second drain opening. The method further comprises simultaneously forming first and second source and drain features in the respective first and second source and drain openings, and forming a protection layer over the dielectric layer, the protection layer including a first gate opening between the first source feature and first drain feature and a second gate opening between the second source feature and the second drain feature. The method further comprises forming a gate dielectric layer in the first gate opening, and simultaneously forming a first gate electrode in the first gate opening and a second gate electrode in the second gate opening, wherein the gate dielectric is interposed between the first gate electrode and the third III-V compound layer, and wherein the second gate electrode contacts the third III-V compound layer.

In another embodiment, a semiconductor structure includes a first III-V layer and a second III-V layer disposed on the first III-V layer. The second III-V layer is different from the first III-V layer. A third III-V layer is disposed on the second III-V layer. A source feature and a drain feature are disposed in a metal-insulator-semiconductor field-effect transistor (MISFET) region over the third III-V layer. A source feature and a drain feature are disposed in a high electron mobility transistor (HEMT) region over the third III-V layer. A gate electrode is disposed over the third III-V layer in the MISFET region, and a gate dielectric layer is disposed below the gate electrode and above the top surface of the third III-V layer. The gate dielectric layer separates the gate electrode from the third III-V layer.

In yet another embodiment, a semiconductor structure includes a stack of semiconductor layers over a substrate. Each semiconductor layer in the stack of semiconductor layers has a different band gap than an adjacent semiconductor layer in the stack. A capping layer is disposed over the stack of semiconductor layers. The capping layer has a first source opening, a first drain opening, a second source opening, and a second drain opening. A first source feature is in the first source opening, a first drain feature is in the first drain opening, a second source feature is in the second source opening, and a second drain feature is in the second drain opening. The first source feature and the first drain feature are disposed in a metal-insulator-semiconductor field-effect transistor (MISFET) region over an uppermost semiconductor layer in the stack of semiconductor layers, and the second source feature and the second drain feature are disposed in a high electron mobility transistor (HEMT) region over the uppermost semiconductor layer in the stack of semiconductor layers. A first gate opening is in the capping layer between the first source feature and the first drain feature. A gate dielectric layer is in the first gate opening. A second gate opening is in the capping layer between the second source feature and the second drain feature. A gate electrode layer is in the first gate opening and the second gate opening.

In still another embodiment, a semiconductor device includes a stack of semiconductor layers over a substrate, where each layer in the stack has a different band gap than an adjacent layer in the stack. A patterned capping layer is disposed over the stack of semiconductor layers. The patterned capping layer has a first source opening, a first drain opening, a second source opening, and a second drain opening. A first source feature is in the first source opening, a first drain feature is in the first drain opening, a second source feature is in the second source opening, and a second drain feature is in the second drain opening. A patterned protection layer is disposed over the patterned capping layer. The patterned protection layer has a first gate opening interjacent the first source feature and first drain feature. A patterned gate dielectric layer is in the first gate opening. A second gate opening is in the patterned protection layer. A gate electrode layer is in the first gate opening and the second gate opening. A portion of the patterned gate dielectric layer is interposed between a first bottom-most surface of the gate electrode layer in the first gate opening and a first portion of an uppermost surface of the stack of semiconductor layers. A second bottom-most surface of the gate electrode layer in the second gate opening is in contact with a second portion of the uppermost surface of the stack of semiconductor layers.

Although the embodiments and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 

What is claimed is:
 1. A semiconductor structure comprising: a first semiconductor layer; a first dielectric layer over the first semiconductor layer; a first source feature and a first drain feature disposed in a metal-insulator-semiconductor field-effect transistor (MISFET) region, the first source feature and the first drain feature comprising a first metal feature extending through the first dielectric layer to the first semiconductor layer; a second source feature and a second drain feature disposed in a high electron mobility transistor (HEMT) region, the second source feature and the second drain feature comprising a second metal feature extending through the first dielectric layer to the first semiconductor layer; a first gate structure in the MISFET region, the first gate structure comprising a gate dielectric and a first gate electrode over the gate dielectric, the gate dielectric extending through the first dielectric layer to the first semiconductor layer; a second gate electrode in the HEMT region, wherein the second gate electrode extends through the first dielectric layer to the first semiconductor layer; and a second dielectric layer over the first dielectric layer, wherein the second dielectric layer extends over at least a portion of the first metal feature along a direction orthogonal to an upper surface of the first dielectric layer, wherein the first gate structure extends over at least a portion of the second dielectric layer along a direction orthogonal to the upper surface of the first dielectric layer.
 2. The semiconductor structure of claim 1, wherein the second dielectric layer extends over at least a portion of the second source feature or the second drain feature.
 3. The semiconductor structure of claim 1, wherein the second gate electrode extends over at least a portion of the second dielectric layer.
 4. The semiconductor structure of claim 3, further comprising a dielectric feature, the dielectric feature being interposed between the second dielectric layer and the second gate electrode.
 5. The semiconductor structure of claim 4, wherein the dielectric feature is formed of a same material as the gate dielectric.
 6. A semiconductor structure comprising: a plurality of semiconductor layers, each semiconductor layer having a different band gap than an adjacent semiconductor layer of the plurality of semiconductor layers; a capping layer over the plurality of semiconductor layers; a first source feature, a first drain feature, a second source feature, and a second drain feature extending through the capping layer to a first semiconductor layer of the plurality of semiconductor layers; a protection layer over the capping layer; a first gate structure extending through the protection layer and the capping layer, the first gate structure comprising a gate dielectric layer and a first gate electrode over the gate dielectric layer, wherein a bottommost surface of the first gate structure contacts an upper surface of an uppermost semiconductor layer of the plurality of semiconductor layers; and a second gate electrode extending through the protection layer and the capping layer.
 7. The semiconductor structure of claim 6, wherein a bottommost surface of the second gate electrode contacts the upper surface of the uppermost semiconductor layer of the plurality of semiconductor layers.
 8. The semiconductor structure of claim 7, further comprising a dielectric feature interposed between the second gate electrode and the protection layer, wherein the dielectric feature and the gate dielectric layer comprise a same material.
 9. The semiconductor structure of claim 6, wherein the plurality of semiconductor layers comprises: a first GaN layer; a first AlGaN layer over the first GaN layer; a second GaN layer over the first AlGaN layer; and a second AlGaN layer over the second GaN layer.
 10. The semiconductor structure of claim 6, wherein the first gate structure and the second gate electrode extend over at least a portion of the protection layer.
 11. The semiconductor structure of claim 10, wherein the protection layer extends over at least a portion of the first source feature, the first drain feature, the second source feature, and the second drain feature.
 12. The semiconductor structure of claim 6, wherein the first source feature, the first drain feature, the second source feature, and the second drain feature contact an uppermost surface of the plurality of semiconductor layers.
 13. A semiconductor device comprising: a first semiconductor layer over a second semiconductor layer, the first semiconductor layer and the second semiconductor layer having a different band gap; a capping layer over the first semiconductor layer; first source/drain elements and second source/drain elements, each of the first source/drain elements and the second source/drain elements extending through the capping layer to the first semiconductor layer; a first gate structure interposed between the first source/drain elements, the first gate structure comprising a gate dielectric having a bottom surface contacting an upper surface of the first semiconductor layer; and a second gate structure interposed between the second source/drain elements, the second gate structure comprising a gate electrode having a bottom surface contacting the upper surface of the first semiconductor layer.
 14. The semiconductor device of claim 1, wherein the second semiconductor layer is over a third semiconductor layer, the second semiconductor layer and the third semiconductor layer having a different band gap.
 15. The semiconductor device of claim 14, wherein the first semiconductor layer and the third semiconductor layer are formed of a same material.
 16. The semiconductor device of claim 13, wherein the first semiconductor layer, the second semiconductor layer are formed of group III-V compounds.
 17. The semiconductor device of claim 13, further comprising a dielectric layer over the capping layer, wherein the first gate structure and the second gate structure extends through the dielectric layer.
 18. The semiconductor device of claim 13, wherein the first source/drain elements and the second source/drain elements contact the first semiconductor layer.
 19. The semiconductor structure of claim 1, wherein a bottommost surface of the first gate structure contacts an upper surface of the first semiconductor layer.
 20. The semiconductor structure of claim 1, wherein a bottommost surface of the second gate electrode contacts an upper surface of the first semiconductor layer. 